1. Field of the Invention
This invention relates to a data processing apparatus for controlling the data bus, address bus, and control signal buses for connecting a data processor with memory devices as objects to be accessible by the data processor, peripheral devices, or other data processors.
2. Description of the related art
In connecting a data processor to an external memory, peripheral devices, or other data processors of the type different from the former-recited data processor, a general-purpose type control system is used, which is independent of the objects to be accessed. When the accessed objects are memories, signals adaptable for these memories and a control system are used. Particularly, the latter system minimizes the additional circuits required for connection.
In the network control system, there are frequent cases that the programs stored in a ROM coexist with a large amount of data to be read out of and written into a memory, or that only the initializing program is stored in the ROM, and the program to be executed is read out from other devices by using the initializing program. In such cases, different types of memories, such as ROM, static RAM, dynamic RAM and the like coexist in the network control system. Consequently, it is impossible to use the control system adapted for only specific types of memories. To cope with this problem, a processor with general purpose control system is used, and further a circuit for generating control signals adapted for these types of memories must be installed in the memory system. The additional circuit is complicated in circuit construction. Further, since it is assembled into the memory system, the number of parts and the circuit mounting area are increased in constructing the network control system. Further, an access time to the memory is increased by the operating time of the additional circuit.
When the control system for specific memories is used, the output mode of an address signal and the control signal differ with the types of the accessed objects. Therefore, the required number of bus control signal lines and external terminals are increased. In this respect, this control system cannot be employed for the processor IC having only the required number of external terminals. The same problem is found in the connection of the data processor, and peripheral devices, and other types of data processors.
As described above, in the conventional bus control system, when the data processor is connected to other devices, the additional circuit is complicated in circuit construction, increasing the number of parts required, the required circuit area, and the access time to the memory.